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-- Company: 
-- Engineer:
--
-- Create Date:   13:01:37 03/14/2012
-- Design Name:   
-- Module Name:   C:/Dropbox/KernfaseProject 34/VHDL/uartram-id/verwerking_tb.vhd
-- Project Name:  uartram-id
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Uartverwerking
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY verwerking_tb IS
END verwerking_tb;
 
ARCHITECTURE behavior OF verwerking_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Uartverwerking
    PORT(
         clk_50MHz : IN  std_logic;
         done : IN  std_logic;
         READ_RAM16x8data : IN  std_logic_vector(7 downto 0);
         READ_RAM16x8addr : OUT  std_logic_vector(3 downto 0);
         Write_idram_en : OUT  std_logic;
         write_idram_data : OUT  std_logic_vector(5 downto 0);
         Write_idram_addr : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk_50MHz : std_logic := '0';
   signal done : std_logic := '0';
   signal READ_RAM16x8data : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal READ_RAM16x8addr : std_logic_vector(3 downto 0);
   signal Write_idram_en : std_logic;
   signal write_idram_data : std_logic_vector(5 downto 0);
   signal Write_idram_addr : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_50MHz_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Uartverwerking PORT MAP (
          clk_50MHz => clk_50MHz,
          done => done,
          READ_RAM16x8data => READ_RAM16x8data,
          READ_RAM16x8addr => READ_RAM16x8addr,
          Write_idram_en => Write_idram_en,
          write_idram_data => write_idram_data,
          Write_idram_addr => Write_idram_addr
        );

   -- Clock process definitions
   clk_50MHz_process :process
   begin
		clk_50MHz <= '0';
		wait for clk_50MHz_period/2;
		clk_50MHz <= '1';
		wait for clk_50MHz_period/2;
   end process;
	
	ramprocess : process (clk_50MHz)
	begin
		if rising_edge(clk_50MHz) then
		READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--			case (READ_RAM16x8addr) is
--				when "0000" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0001" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0010" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0011" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0100" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0101" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0110" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "0111" => READ_RAM16X8DATA <= "0000" & READ_RAM16X8ADDR;
--				when "1000" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1001" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1010" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1011" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1100" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1101" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1110" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when "1111" => READ_RAM16X8DATA <= std_logic_vector(to_unsigned(read_ram16x8addr,8));
--				when others => "0000" & READ_RAM16X8ADDR;
--			end case;
		end if;
	end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_50MHz_period*10;
		
		

			DONE <= '1';-- insert stimulus here 

			--READ_RAM16X8ADDR <= "

      wait;
   end process;

END;
